nanoREV.

Nanoimprint Lithography Stamps Out Semiconductor Processing Steps

Patterning the insulating layers on silicon wafers via photolithography is becoming increasingly difficult at the nano length scale. The conventional process, consisting of several masking, depositing and etching steps to form trenches and conductive pathways is prone to errors due to the fine details of the patterns not translating well at these smaller scales. However, these problems may no longer be as daunting a task when depositing spin-on organosilicate glass (the insulating layer between logic devices and integrated circuits) in future electronics.

In a recent update, the National Institute for Standards and Technology (NIST) announced that it has helped develop a promising advancement in nanolithography. Using a stamping method in which a die comprising the pattern to be formed is pressed against the soft insulating material, NIST scientists confirmed they were able to transfer patterns with details less than 100 nanometers. Additionally, the stamping process does not seem to cause significant damage to the nanoporous framework through which copper interconnects are formed. In a surprising twist, the nanolithography process actually increased the density of the nanopores. The results are significant as they point to improved performance, fewer short circuits and a lot fewer processing steps for future semiconductor based circuitry.

See the complete media release.